Regviz

Nordic Semiconductor /nrf52840 /RADIO /INTENCLR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTENCLR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Nordic Semiconductor/nrf52840/RADIO/INTENCLR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disabled)READY 0 (Disabled)ADDRESS 0 (Disabled)PAYLOAD 0 (Disabled)END 0 (Disabled)DISABLED 0 (Disabled)DEVMATCH 0 (Disabled)DEVMISS 0 (Disabled)RSSIEND 0 (Disabled)BCMATCH 0 (Disabled)CRCOK 0 (Disabled)CRCERROR 0 (Disabled)FRAMESTART 0 (Disabled)EDEND 0 (Disabled)EDSTOPPED 0 (Disabled)CCAIDLE 0 (Disabled)CCABUSY 0 (Disabled)CCASTOPPED 0 (Disabled)RATEBOOST 0 (Disabled)TXREADY 0 (Disabled)RXREADY 0 (Disabled)MHRMATCH 0 (Disabled)SYNC 0 (Disabled)PHYEND

BCMATCH=Disabled, ADDRESS=Disabled, FRAMESTART=Disabled, RXREADY=Disabled, READY=Disabled, CRCERROR=Disabled, CCABUSY=Disabled, PHYEND=Disabled, DEVMISS=Disabled, PAYLOAD=Disabled, CRCOK=Disabled, DISABLED=Disabled, RSSIEND=Disabled, END=Disabled, DEVMATCH=Disabled, SYNC=Disabled, RATEBOOST=Disabled, EDEND=Disabled, TXREADY=Disabled, CCASTOPPED=Disabled, EDSTOPPED=Disabled, MHRMATCH=Disabled, CCAIDLE=Disabled

Description

Disable interrupt

Fields

READY

Write ‘1’ to disable interrupt for event READY

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
ADDRESS

Write ‘1’ to disable interrupt for event ADDRESS

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
PAYLOAD

Write ‘1’ to disable interrupt for event PAYLOAD

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
END

Write ‘1’ to disable interrupt for event END

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
DISABLED

Write ‘1’ to disable interrupt for event DISABLED

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
DEVMATCH

Write ‘1’ to disable interrupt for event DEVMATCH

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
DEVMISS

Write ‘1’ to disable interrupt for event DEVMISS

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
RSSIEND

Write ‘1’ to disable interrupt for event RSSIEND

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
BCMATCH

Write ‘1’ to disable interrupt for event BCMATCH

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CRCOK

Write ‘1’ to disable interrupt for event CRCOK

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CRCERROR

Write ‘1’ to disable interrupt for event CRCERROR

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
FRAMESTART

Write ‘1’ to disable interrupt for event FRAMESTART

0 (Disabled): Read: Disabled

1 (Enabled): Read: Enabled

1 (Clear): Disable
EDEND

Write ‘1’ to disable interrupt for event EDEND

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
EDSTOPPED

Write ‘1’ to disable interrupt for event EDSTOPPED

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CCAIDLE

Write ‘1’ to disable interrupt for event CCAIDLE

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CCABUSY

Write ‘1’ to disable interrupt for event CCABUSY

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
CCASTOPPED

Write ‘1’ to disable interrupt for event CCASTOPPED

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
RATEBOOST

Write ‘1’ to disable interrupt for event RATEBOOST

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
TXREADY

Write ‘1’ to disable interrupt for event TXREADY

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
RXREADY

Write ‘1’ to disable interrupt for event RXREADY

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
MHRMATCH

Write ‘1’ to disable interrupt for event MHRMATCH

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
SYNC

Write ‘1’ to disable interrupt for event SYNC

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled
PHYEND

Write ‘1’ to disable interrupt for event PHYEND

0 (Disabled): Read: Disabled

1 (Clear): Disable

1 (Enabled): Read: Enabled

Links

()

Register License

Copyright © 2010 - 2021, Nordic Semiconductor ASA All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

  3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data